Aiming for a high-speed highly-integrated non-volatile memory, phase-change memories are under development, as described in “2002 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 202-203”. In the phase-change memory, data is stored by taking advantage of the characteristic that a phase-change material called chalcogenide material has different resistances depending on its condition. Rewriting of a phase-change resistor is performed by changing the conditions by applying electric current so as to generate heat. Increasing resistance (transition to amorphous state) which is called RESET operation is carried out by maintaining a comparatively high temperature, and reducing resistance (crystallization) which is called SET operation is carried out by maintaining a comparatively low temperature for enough period of time. Reading out operation of the phase-change material is carried out by applying electric current in the degree that does not change the state of the phase-change resistor.
The characteristics of phase-change resistor are described in
“2002 IEEE International Electron Devices Meeting, Technical Digest, pp. 923-926” and the Japanese Patent Application Laid-Open No. 2003-100084. In addition, a memory cell comprises a phase-change resistor and an NMOS transistor is described in “2003 Non-Volatile Semiconductor Memory Workshop, Digest of Technical Papers, pp. 91-92”.
In these documents, not only a high speed ROM (Read-Only Memory) but also the possibility of non-volatile RAM (Random Access Memory) is described, and realization of an integrated type memory which has both functions of ROM and RAM is mentioned. In a phase-change memory having small electrode area of a phase-change resistor, resistance value can be changed with a little electricity, therefore scaling of a cell is easy. In addition, a high-speed reading operation can be realized since the resistance value difference in amorphous state and crystalline state is large. Because of the above described reasons, realization of a high-speed non-volatile memory employing a phase-change memory has been expected.
In the Japanese Patent Application Laid-Open No. 2003-229537, a memory cell structure employing a phase-change resistor and a vertical transistor is described. A memory cell having small area compare with conventional DRAM is realized by employing the memory cell structure.